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<title>PSADBW—Compute Sum of Absolute Differences </title></head>
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<h1>PSADBW—Compute Sum of Absolute Differences</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F F6 /<em>r</em><sup>1</sup></p>
<p>PSADBW <em>mm1, mm2/m64</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE</td>
<td>Computes the absolute differences of the packed unsigned byte integers from <em>mm2 /m64</em> and <em>mm1</em>; differences are then summed to produce an unsigned word integer result.</td></tr>
<tr>
<td>
<p>66 0F F6 /<em>r</em></p>
<p>PSADBW <em>xmm1</em>, <em>xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Computes the absolute differences of the packed unsigned byte integers from <em>xmm2 /m128</em> and <em>xmm1</em>; the 8 low differences and 8 high differences are then summed separately to produce two unsigned word integer results.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F.WIG F6 /r</p>
<p>VPSADBW <em>xmm1, xmm2, xmm3/m128</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Computes the absolute differences of the packed unsigned byte integers from <em>xmm3 /m128</em> and <em>xmm2</em>; the 8 low differences and 8 high differences are then summed separately to produce two unsigned word integer results.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F.WIG F6 /r</p>
<p>VPSADBW<em> ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Computes the absolute differences of the packed unsigned byte integers from <em>ymm3 /m256</em> and <em>ymm2</em>; then each consecutive 8 differences are summed separately to produce four unsigned word integer results.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.WIG F6 /r</p>
<p>VPSADBW xmm1, xmm2, xmm3/m128</p></td>
<td>FVM</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512BW</p></td>
<td>Computes the absolute differences of the packed unsigned byte integers from xmm3 /m128 and xmm2; then each consecutive 8 differences are summed separately to produce four unsigned word integer results.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.WIG F6 /r</p>
<p>VPSADBW ymm1, ymm2, ymm3/m256</p></td>
<td>FVM</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512BW</p></td>
<td>Computes the absolute differences of the packed unsigned byte integers from ymm3 /m256 and ymm2; then each consecutive 8 differences are summed separately to produce four unsigned word integer results.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F.WIG F6 /r</p>
<p>VPSADBW zmm1, zmm2, zmm3/m512</p></td>
<td>FVM</td>
<td>V/V</td>
<td>AVX512BW</td>
<td>Computes the absolute differences of the packed unsigned byte integers from zmm3 /m512 and zmm2; then each consecutive 8 differences are summed separately to produce four unsigned word integer results.</td></tr></table>
<p>NOTES:</p>
<p>1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FVM</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Computes the absolute value of the difference of 8 unsigned byte integers from the source operand (second</p>
<p>operand) and from the destination operand (first operand). These 8 differences are then summed to produce an unsigned word integer result that is stored in the destination operand. Figure 4-14 shows the operation of the PSADBW instruction when using 64-bit operands.</p>
<p>When operating on 64-bit operands, the word integer result is stored in the low word of the destination operand, and the remaining bytes in the destination operand are cleared to all 0s.</p>
<p>When operating on 128-bit operands, two packed results are computed. Here, the 8 low-order bytes of the source and destination operands are operated on to produce a word result that is stored in the low word of the destination operand, and the 8 high-order bytes are operated on to produce a word result that is stored in bits 64 through 79 of the destination operand. The remaining bytes of the destination operand are cleared.</p>
<p>For 256-bit version, the third group of 8 differences are summed to produce an unsigned word in bits[143:128] of the destination register and the fourth group of 8 differences are summed to produce an unsigned word in bits[207:192] of the destination register. The remaining words of the destination are set to 0.</p>
<p>For 512-bit version, the fifth group result is stored in bits [271:256] of the destination. The result from the sixth group is stored in bits [335:320]. The results for the seventh and eighth group are stored respectively in bits [399:384] and bits [463:447], respectively. The remaining bits in the destination are set to 0.</p>
<p>In 64-bit mode and not encoded by VEX/EVEX prefix, using a REX prefix in the form of REX.R permits this instruc-tion to access additional registers (XMM8-XMM15).</p>
<p>Legacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an MMX technology register.</p>
<p>128-bit Legacy SSE version: The first source operand and destination register are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain unchanged.</p>
<p>VEX.128 and EVEX.128 encoded versions: The first source operand and destination register are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corre-sponding ZMM register are zeroed.</p>
<p>VEX.256 and EVEX.256 encoded versions: The first source operand and destination register are YMM registers. The second source operand is an YMM register or a 256-bit memory location. Bits (MAX_VL-1:256) of the corre-sponding ZMM register are zeroed.</p>
<p>EVEX.512 encoded version: The first source operand and destination register are ZMM registers. The second source operand is a ZMM register or a 512-bit memory location.</p>
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<h3>Figure 4-14.  PSADBW Instruction Operation Using 64-bit Operands</h3>
<h2>Operation</h2>
<p><strong>VPSADBW (EVEX encoded versions)</strong></p>
<pre>VL = 128, 256, 512
TEMP0 (cid:197) ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 1 through 15 *)
TEMP15 (cid:197) ABS(SRC1[127:120] - SRC2[127:120])
DEST[15:0] (cid:197)SUM(TEMP0:TEMP7)
DEST[63:16] (cid:197) 000000000000H
DEST[79:64] (cid:197) SUM(TEMP8:TEMP15)
DEST[127:80] (cid:197) 00000000000H
IF VL &gt;= 256
    (* Repeat operation for bytes 16 through 31*)
    TEMP31 (cid:197) ABS(SRC1[255:248] - SRC2[255:248])
    DEST[143:128] (cid:197)SUM(TEMP16:TEMP23)
    DEST[191:144] (cid:197) 000000000000H
    DEST[207:192] (cid:197) SUM(TEMP24:TEMP31)
    DEST[223:208] (cid:197) 00000000000H
FI;
IF VL &gt;= 512
(* Repeat operation for bytes 32 through 63*)
    TEMP63 (cid:197) ABS(SRC1[511:504] - SRC2[511:504])
    DEST[271:256] (cid:197)SUM(TEMP0:TEMP7)
    DEST[319:272] (cid:197) 000000000000H
    DEST[335:320] (cid:197) SUM(TEMP8:TEMP15)
    DEST[383:336] (cid:197) 00000000000H
    DEST[399:384] (cid:197)SUM(TEMP16:TEMP23)
    DEST[447:400] (cid:197) 000000000000H
    DEST[463:448] (cid:197) SUM(TEMP24:TEMP31)
    DEST[511:464] (cid:197) 00000000000H
FI;
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<p><strong>VPSADBW (VEX.256 encoded version)</strong></p>
<pre>TEMP0 (cid:197) ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 2 through 30*)
TEMP31 (cid:197) ABS(SRC1[255:248] - SRC2[255:248])
DEST[15:0] (cid:197)SUM(TEMP0:TEMP7)
DEST[63:16] (cid:197) 000000000000H
DEST[79:64] (cid:197) SUM(TEMP8:TEMP15)
DEST[127:80] (cid:197) 00000000000H
DEST[143:128] (cid:197)SUM(TEMP16:TEMP23)
DEST[191:144] (cid:197) 000000000000H
DEST[207:192] (cid:197) SUM(TEMP24:TEMP31)
DEST[223:208] (cid:197) 00000000000H
DEST[MAX_VL-1:256] (cid:197) 0</pre>
<p><strong>VPSADBW (VEX.128 encoded version)</strong></p>
<pre>TEMP0 (cid:197) ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 2 through 14 *)
TEMP15 (cid:197) ABS(SRC1[127:120] - SRC2[127:120])
DEST[15:0] (cid:197)SUM(TEMP0:TEMP7)
DEST[63:16] (cid:197) 000000000000H
DEST[79:64] (cid:197) SUM(TEMP8:TEMP15)
DEST[127:80] (cid:197) 00000000000H
DEST[MAX_VL-1:128] (cid:197) 0</pre>
<p><strong>PSADBW (128-bit Legacy SSE version)</strong></p>
<pre>TEMP0 (cid:197) ABS(DEST[7:0] - SRC[7:0])
(* Repeat operation for bytes 2 through 14 *)
TEMP15 (cid:197) ABS(DEST[127:120] - SRC[127:120])
DEST[15:0] (cid:197)SUM(TEMP0:TEMP7)
DEST[63:16] (cid:197) 000000000000H
DEST[79:64] (cid:197) SUM(TEMP8:TEMP15)
DEST[127:80] (cid:197) 00000000000
DEST[MAX_VL-1:128] (Unmodified)</pre>
<p><strong>PSADBW (64-bit operand)</strong></p>
<pre>TEMP0 (cid:197) ABS(DEST[7:0] - SRC[7:0])
(* Repeat operation for bytes 2 through 6 *)
TEMP7 (cid:197) ABS(DEST[63:56] - SRC[63:56])
DEST[15:0] (cid:197)SUM(TEMP0:TEMP7)
DEST[63:16] (cid:197) 000000000000H</pre>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<pre>VPSADBW __m512i _mm512_sad_epu8( __m512i a, __m512i b)
PSADBW:__m64 _mm_sad_pu8(__m64 a,__m64 b)
(V)PSADBW:__m128i _mm_sad_epu8(__m128i a, __m128i b)
VPSADBW:__m256i _mm256_sad_epu8( __m256i a, __m256i b)</pre>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None.</p>
<h2>Other Exceptions</h2>
<p>Non-EVEX-encoded instruction, see Exceptions Type 4.</p>
<p>EVEX-encoded instruction, see Exceptions Type E4NF.nb.</p></body></html>